// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  pack_info_reg_reg_offset_field.h
// Project line  :  Platform & Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 17:53:04 Create file
// ******************************************************************************

#ifndef __PACK_INFO_REG_REG_OFFSET_FIELD_H__
#define __PACK_INFO_REG_REG_OFFSET_FIELD_H__

#define PACK_INFO_REG_DDR_PWRDN_TIME_EN_LEN    1
#define PACK_INFO_REG_DDR_PWRDN_TIME_EN_OFFSET 7
#define PACK_INFO_REG_DDR_PATTERN_EN_LEN       1
#define PACK_INFO_REG_DDR_PATTERN_EN_OFFSET    6
#define PACK_INFO_REG_DDR_PWRDN_EN_LEN         1
#define PACK_INFO_REG_DDR_PWRDN_EN_OFFSET      5
#define PACK_INFO_REG_DDR_SR_EN_LEN            1
#define PACK_INFO_REG_DDR_SR_EN_OFFSET         4
#define PACK_INFO_REG_DDR_STCHANGE_EN_LEN      1
#define PACK_INFO_REG_DDR_STCHANGE_EN_OFFSET   3
#define PACK_INFO_REG_FAST_TRAIN_EN_LEN        1
#define PACK_INFO_REG_FAST_TRAIN_EN_OFFSET     2
#define PACK_INFO_REG_RE_TRAIN_EN_LEN          1
#define PACK_INFO_REG_RE_TRAIN_EN_OFFSET       1
#define PACK_INFO_REG_INIT_TRAIN_EN_LEN        1
#define PACK_INFO_REG_INIT_TRAIN_EN_OFFSET     0

#define PACK_INFO_REG_MSGTYPE_INFO_LEN      8
#define PACK_INFO_REG_MSGTYPE_INFO_OFFSET   24
#define PACK_INFO_REG_SESSIONID_INFO_LEN    8
#define PACK_INFO_REG_SESSIONID_INFO_OFFSET 16
#define PACK_INFO_REG_SERVICEID_INFO_LEN    16
#define PACK_INFO_REG_SERVICEID_INFO_OFFSET 0

#define PACK_INFO_REG_TRANS_ID_LEN    32
#define PACK_INFO_REG_TRANS_ID_OFFSET 0

#define PACK_INFO_REG_BBP_ID_LEN    32
#define PACK_INFO_REG_BBP_ID_OFFSET 0

#define PACK_INFO_REG_MAGIC_ID_LEN    32
#define PACK_INFO_REG_MAGIC_ID_OFFSET 0

#define PACK_INFO_REG_TIMESTAMP_H_LEN    32
#define PACK_INFO_REG_TIMESTAMP_H_OFFSET 0

#define PACK_INFO_REG_TIMESTAMP_L_LEN    32
#define PACK_INFO_REG_TIMESTAMP_L_OFFSET 0

#define PACK_INFO_REG_WREN_P0P1_DIFF_LEN    1
#define PACK_INFO_REG_WREN_P0P1_DIFF_OFFSET 11
#define PACK_INFO_REG_WREN_P1_DIFF_LEN      1
#define PACK_INFO_REG_WREN_P1_DIFF_OFFSET   10
#define PACK_INFO_REG_WREN_P0_DIFF_LEN      1
#define PACK_INFO_REG_WREN_P0_DIFF_OFFSET   9
#define PACK_INFO_REG_CA_GAP_TIMEOUT_LEN    1
#define PACK_INFO_REG_CA_GAP_TIMEOUT_OFFSET 8
#define PACK_INFO_REG_AHB_ERROR_LEN         1
#define PACK_INFO_REG_AHB_ERROR_OFFSET      5
#define PACK_INFO_REG_FRAME_ERROR_LEN       1
#define PACK_INFO_REG_FRAME_ERROR_OFFSET    4
#define PACK_INFO_REG_UCE_ID_LEN            2
#define PACK_INFO_REG_UCE_ID_OFFSET         0

#define PACK_INFO_REG_UCE_WLRL_CFG_LEN    32
#define PACK_INFO_REG_UCE_WLRL_CFG_OFFSET 0

#define PACK_INFO_REG_CA_TIMEOUT_LEN    31
#define PACK_INFO_REG_CA_TIMEOUT_OFFSET 0

#define PACK_INFO_REG_BACKFORCE_NUM_LEN    32
#define PACK_INFO_REG_BACKFORCE_NUM_OFFSET 0

#define PACK_INFO_REG_UFINFO_ADDR_PATTN0_LEN    32
#define PACK_INFO_REG_UFINFO_ADDR_PATTN0_OFFSET 0

#define PACK_INFO_REG_UFINFO_ADDR_PATTN1_LEN    32
#define PACK_INFO_REG_UFINFO_ADDR_PATTN1_OFFSET 0

#define PACK_INFO_REG_UFINFO_ADDR_PATTN2_LEN    32
#define PACK_INFO_REG_UFINFO_ADDR_PATTN2_OFFSET 0

#define PACK_INFO_REG_UFINFO_ADDR_PATTN3_LEN    32
#define PACK_INFO_REG_UFINFO_ADDR_PATTN3_OFFSET 0

#define PACK_INFO_REG_UFINFO_ADDR_PATTN4_LEN    32
#define PACK_INFO_REG_UFINFO_ADDR_PATTN4_OFFSET 0

#define PACK_INFO_REG_UINFO_CA_TIME01_LEN    31
#define PACK_INFO_REG_UINFO_CA_TIME01_OFFSET 0

#define PACK_INFO_REG_UINFO_CA_TIME12_LEN    31
#define PACK_INFO_REG_UINFO_CA_TIME12_OFFSET 0

#define PACK_INFO_REG_UINFO_CA_TIME23_LEN    31
#define PACK_INFO_REG_UINFO_CA_TIME23_OFFSET 0

#define PACK_INFO_REG_UINFO_CA_TIME34_LEN    31
#define PACK_INFO_REG_UINFO_CA_TIME34_OFFSET 0

#define PACK_INFO_REG_ADDR_NUM_LEN     3
#define PACK_INFO_REG_ADDR_NUM_OFFSET  4
#define PACK_INFO_REG_ADDR_RANK_LEN    2
#define PACK_INFO_REG_ADDR_RANK_OFFSET 0

#define PACK_INFO_REG_ADDR_BL_SEL_LEN    1
#define PACK_INFO_REG_ADDR_BL_SEL_OFFSET 2
#define PACK_INFO_REG_IN_DFS_SEL_LEN     1
#define PACK_INFO_REG_IN_DFS_SEL_OFFSET  1

#define PACK_INFO_REG_WREN_P31_NUM_LEN    4
#define PACK_INFO_REG_WREN_P31_NUM_OFFSET 28
#define PACK_INFO_REG_WREN_P30_NUM_LEN    4
#define PACK_INFO_REG_WREN_P30_NUM_OFFSET 24
#define PACK_INFO_REG_WREN_P21_NUM_LEN    4
#define PACK_INFO_REG_WREN_P21_NUM_OFFSET 20
#define PACK_INFO_REG_WREN_P20_NUM_LEN    4
#define PACK_INFO_REG_WREN_P20_NUM_OFFSET 16
#define PACK_INFO_REG_WREN_P11_NUM_LEN    4
#define PACK_INFO_REG_WREN_P11_NUM_OFFSET 12
#define PACK_INFO_REG_WREN_P10_NUM_LEN    4
#define PACK_INFO_REG_WREN_P10_NUM_OFFSET 8
#define PACK_INFO_REG_WREN_P01_NUM_LEN    4
#define PACK_INFO_REG_WREN_P01_NUM_OFFSET 4
#define PACK_INFO_REG_WREN_P00_NUM_LEN    4
#define PACK_INFO_REG_WREN_P00_NUM_OFFSET 0

#define PACK_INFO_REG_WDM_P13_NUM_LEN    4
#define PACK_INFO_REG_WDM_P13_NUM_OFFSET 28
#define PACK_INFO_REG_WDM_P12_NUM_LEN    4
#define PACK_INFO_REG_WDM_P12_NUM_OFFSET 24
#define PACK_INFO_REG_WDM_P11_NUM_LEN    4
#define PACK_INFO_REG_WDM_P11_NUM_OFFSET 20
#define PACK_INFO_REG_WDM_P10_NUM_LEN    4
#define PACK_INFO_REG_WDM_P10_NUM_OFFSET 16
#define PACK_INFO_REG_WDM_P03_NUM_LEN    4
#define PACK_INFO_REG_WDM_P03_NUM_OFFSET 12
#define PACK_INFO_REG_WDM_P02_NUM_LEN    4
#define PACK_INFO_REG_WDM_P02_NUM_OFFSET 8
#define PACK_INFO_REG_WDM_P01_NUM_LEN    4
#define PACK_INFO_REG_WDM_P01_NUM_OFFSET 4
#define PACK_INFO_REG_WDM_P00_NUM_LEN    4
#define PACK_INFO_REG_WDM_P00_NUM_OFFSET 0

#define PACK_INFO_REG_WDATA_P13_NUM_LEN    4
#define PACK_INFO_REG_WDATA_P13_NUM_OFFSET 28
#define PACK_INFO_REG_WDATA_P12_NUM_LEN    4
#define PACK_INFO_REG_WDATA_P12_NUM_OFFSET 24
#define PACK_INFO_REG_WDATA_P11_NUM_LEN    4
#define PACK_INFO_REG_WDATA_P11_NUM_OFFSET 20
#define PACK_INFO_REG_WDATA_P10_NUM_LEN    4
#define PACK_INFO_REG_WDATA_P10_NUM_OFFSET 16
#define PACK_INFO_REG_WDATA_P03_NUM_LEN    4
#define PACK_INFO_REG_WDATA_P03_NUM_OFFSET 12
#define PACK_INFO_REG_WDATA_P02_NUM_LEN    4
#define PACK_INFO_REG_WDATA_P02_NUM_OFFSET 8
#define PACK_INFO_REG_WDATA_P01_NUM_LEN    4
#define PACK_INFO_REG_WDATA_P01_NUM_OFFSET 4
#define PACK_INFO_REG_WDATA_P00_NUM_LEN    4
#define PACK_INFO_REG_WDATA_P00_NUM_OFFSET 0

#define PACK_INFO_REG_BASE_ADDR_ACT_LEN    24
#define PACK_INFO_REG_BASE_ADDR_ACT_OFFSET 0

#define PACK_INFO_REG_BASE_ADDR_RW_LEN    24
#define PACK_INFO_REG_BASE_ADDR_RW_OFFSET 0

#define PACK_INFO_REG_BASE_ADDR_ABP_LEN    12
#define PACK_INFO_REG_BASE_ADDR_ABP_OFFSET 0

#define PACK_INFO_REG_BASE_ADDR_PBP_LEN    12
#define PACK_INFO_REG_BASE_ADDR_PBP_OFFSET 0

#define PACK_INFO_REG_SECNE7_ADDR_RW_MISMATCH_NUM_LEN    32
#define PACK_INFO_REG_SECNE7_ADDR_RW_MISMATCH_NUM_OFFSET 0

#define PACK_INFO_REG_SAMPLE_CTRL_RESERVED_LEN    30
#define PACK_INFO_REG_SAMPLE_CTRL_RESERVED_OFFSET 2
#define PACK_INFO_REG_SEC5_WDATA_EN_LEN           1
#define PACK_INFO_REG_SEC5_WDATA_EN_OFFSET        1
#define PACK_INFO_REG_SEC5_RDATA_EN_LEN           1
#define PACK_INFO_REG_SEC5_RDATA_EN_OFFSET        0

#define PACK_INFO_REG_SAMPLE_STATE_RESERVED_LEN     17
#define PACK_INFO_REG_SAMPLE_STATE_RESERVED_OFFSET  15
#define PACK_INFO_REG_DFICLK_RATIO_LEN              2
#define PACK_INFO_REG_DFICLK_RATIO_OFFSET           13
#define PACK_INFO_REG_WRG_WLRL_DVALID_LEN           1
#define PACK_INFO_REG_WRG_WLRL_DVALID_OFFSET        12
#define PACK_INFO_REG_BASE_ADDR_DATA_CLK_CNT_LEN    4
#define PACK_INFO_REG_BASE_ADDR_DATA_CLK_CNT_OFFSET 8
#define PACK_INFO_REG_ERR_S5FLAG_REQPOS_LEN         1
#define PACK_INFO_REG_ERR_S5FLAG_REQPOS_OFFSET      6
#define PACK_INFO_REG_ERR_RANK1_CKE_POSNEG_LEN      1
#define PACK_INFO_REG_ERR_RANK1_CKE_POSNEG_OFFSET   5
#define PACK_INFO_REG_ERR_RANK0_CKE_POSNEG_LEN      1
#define PACK_INFO_REG_ERR_RANK0_CKE_POSNEG_OFFSET   4
#define PACK_INFO_REG_ERR_RNK1_CKE_CA_LEN           1
#define PACK_INFO_REG_ERR_RNK1_CKE_CA_OFFSET        3
#define PACK_INFO_REG_ERR_RNK0_CKE_CA_LEN           1
#define PACK_INFO_REG_ERR_RNK0_CKE_CA_OFFSET        2
#define PACK_INFO_REG_ERR_S4FLAG_REQPOS_LEN         1
#define PACK_INFO_REG_ERR_S4FLAG_REQPOS_OFFSET      1
#define PACK_INFO_REG_CMD_ERR_LEN                   1
#define PACK_INFO_REG_CMD_ERR_OFFSET                0

#define PACK_INFO_REG_WDM_P33_NUM_LEN    4
#define PACK_INFO_REG_WDM_P33_NUM_OFFSET 28
#define PACK_INFO_REG_WDM_P32_NUM_LEN    4
#define PACK_INFO_REG_WDM_P32_NUM_OFFSET 24
#define PACK_INFO_REG_WDM_P31_NUM_LEN    4
#define PACK_INFO_REG_WDM_P31_NUM_OFFSET 20
#define PACK_INFO_REG_WDM_P30_NUM_LEN    4
#define PACK_INFO_REG_WDM_P30_NUM_OFFSET 16
#define PACK_INFO_REG_WDM_P23_NUM_LEN    4
#define PACK_INFO_REG_WDM_P23_NUM_OFFSET 12
#define PACK_INFO_REG_WDM_P22_NUM_LEN    4
#define PACK_INFO_REG_WDM_P22_NUM_OFFSET 8
#define PACK_INFO_REG_WDM_P21_NUM_LEN    4
#define PACK_INFO_REG_WDM_P21_NUM_OFFSET 4
#define PACK_INFO_REG_WDM_P20_NUM_LEN    4
#define PACK_INFO_REG_WDM_P20_NUM_OFFSET 0

#define PACK_INFO_REG_WDATA_P33_NUM_LEN    4
#define PACK_INFO_REG_WDATA_P33_NUM_OFFSET 28
#define PACK_INFO_REG_WDATA_P32_NUM_LEN    4
#define PACK_INFO_REG_WDATA_P32_NUM_OFFSET 24
#define PACK_INFO_REG_WDATA_P31_NUM_LEN    4
#define PACK_INFO_REG_WDATA_P31_NUM_OFFSET 20
#define PACK_INFO_REG_WDATA_P30_NUM_LEN    4
#define PACK_INFO_REG_WDATA_P30_NUM_OFFSET 16
#define PACK_INFO_REG_WDATA_P23_NUM_LEN    4
#define PACK_INFO_REG_WDATA_P23_NUM_OFFSET 12
#define PACK_INFO_REG_WDATA_P22_NUM_LEN    4
#define PACK_INFO_REG_WDATA_P22_NUM_OFFSET 8
#define PACK_INFO_REG_WDATA_P21_NUM_LEN    4
#define PACK_INFO_REG_WDATA_P21_NUM_OFFSET 4
#define PACK_INFO_REG_WDATA_P20_NUM_LEN    4
#define PACK_INFO_REG_WDATA_P20_NUM_OFFSET 0

#define PACK_INFO_REG_UINFO_START_ADDR_LEN    32
#define PACK_INFO_REG_UINFO_START_ADDR_OFFSET 0

#define PACK_INFO_REG_UINFO_END_ADDR_LEN    32
#define PACK_INFO_REG_UINFO_END_ADDR_OFFSET 0

#define PACK_INFO_REG_ARFIFO_CNT_LEN       7
#define PACK_INFO_REG_ARFIFO_CNT_OFFSET    16
#define PACK_INFO_REG_AFIFO_RERROR_LEN     1
#define PACK_INFO_REG_AFIFO_RERROR_OFFSET  13
#define PACK_INFO_REG_AFIFO_RAEMPTY_LEN    1
#define PACK_INFO_REG_AFIFO_RAEMPTY_OFFSET 12
#define PACK_INFO_REG_AFIFO_REMPTY_LEN     1
#define PACK_INFO_REG_AFIFO_REMPTY_OFFSET  11
#define PACK_INFO_REG_AFIFO_RHFULL_LEN     1
#define PACK_INFO_REG_AFIFO_RHFULL_OFFSET  10
#define PACK_INFO_REG_AFIFO_RAFULL_LEN     1
#define PACK_INFO_REG_AFIFO_RAFULL_OFFSET  9
#define PACK_INFO_REG_AFIFO_RFULL_LEN      1
#define PACK_INFO_REG_AFIFO_RFULL_OFFSET   8
#define PACK_INFO_REG_AFIFO_WERROR_LEN     1
#define PACK_INFO_REG_AFIFO_WERROR_OFFSET  5
#define PACK_INFO_REG_AFIFO_WAEMPTY_LEN    1
#define PACK_INFO_REG_AFIFO_WAEMPTY_OFFSET 4
#define PACK_INFO_REG_AFIFO_WEMPTY_LEN     1
#define PACK_INFO_REG_AFIFO_WEMPTY_OFFSET  3
#define PACK_INFO_REG_AFIFO_WHFULL_LEN     1
#define PACK_INFO_REG_AFIFO_WHFULL_OFFSET  2
#define PACK_INFO_REG_AFIFO_WAFULL_LEN     1
#define PACK_INFO_REG_AFIFO_WAFULL_OFFSET  1
#define PACK_INFO_REG_AFIFO_WFULL_LEN      1
#define PACK_INFO_REG_AFIFO_WFULL_OFFSET   0

#define PACK_INFO_REG_UINFO_CFG_ADDR_LEN    32
#define PACK_INFO_REG_UINFO_CFG_ADDR_OFFSET 0

#define PACK_INFO_REG_FIFO_ERROR_RAW_INTR_LEN        1
#define PACK_INFO_REG_FIFO_ERROR_RAW_INTR_OFFSET     3
#define PACK_INFO_REG_INFO_FRM_OVR_RAW_INTR_LEN      1
#define PACK_INFO_REG_INFO_FRM_OVR_RAW_INTR_OFFSET   2
#define PACK_INFO_REG_INFO_FRM_LVL_RAW_INTR_LEN      1
#define PACK_INFO_REG_INFO_FRM_LVL_RAW_INTR_OFFSET   1
#define PACK_INFO_REG_INFO_TRANS_END_RAW_INTR_LEN    1
#define PACK_INFO_REG_INFO_TRANS_END_RAW_INTR_OFFSET 0

#define PACK_INFO_REG_FIFO_ERROR_RAW_INTR_MASK_LEN       1
#define PACK_INFO_REG_FIFO_ERROR_RAW_INTR_MASK_OFFSET    3
#define PACK_INFO_REG_INFO_FRM_OVR_RAW_INTR_MSK_LEN      1
#define PACK_INFO_REG_INFO_FRM_OVR_RAW_INTR_MSK_OFFSET   2
#define PACK_INFO_REG_INFO_FRM_LVL_RAW_INTR_MSK_LEN      1
#define PACK_INFO_REG_INFO_FRM_LVL_RAW_INTR_MSK_OFFSET   1
#define PACK_INFO_REG_INFO_TRANS_END_RAW_INTR_MSK_LEN    1
#define PACK_INFO_REG_INFO_TRANS_END_RAW_INTR_MSK_OFFSET 0

#define PACK_INFO_REG_CFG_CNT_RST_LEN                    1
#define PACK_INFO_REG_CFG_CNT_RST_OFFSET                 8
#define PACK_INFO_REG_FIFO_ERROR_RAW_INTR_CLR_LEN        1
#define PACK_INFO_REG_FIFO_ERROR_RAW_INTR_CLR_OFFSET     3
#define PACK_INFO_REG_INFO_FRM_OVR_RAW_INTR_CLR_LEN      1
#define PACK_INFO_REG_INFO_FRM_OVR_RAW_INTR_CLR_OFFSET   2
#define PACK_INFO_REG_INFO_FRM_LVL_RAW_INTR_CLR_LEN      1
#define PACK_INFO_REG_INFO_FRM_LVL_RAW_INTR_CLR_OFFSET   1
#define PACK_INFO_REG_INFO_TRANS_END_RAW_INTR_CLR_LEN    1
#define PACK_INFO_REG_INFO_TRANS_END_RAW_INTR_CLR_OFFSET 0

#define PACK_INFO_REG_FIFO_ERROR_MSK_INTR_LEN        1
#define PACK_INFO_REG_FIFO_ERROR_MSK_INTR_OFFSET     3
#define PACK_INFO_REG_INFO_FRM_OVR_MSK_INTR_LEN      1
#define PACK_INFO_REG_INFO_FRM_OVR_MSK_INTR_OFFSET   2
#define PACK_INFO_REG_INFO_FRM_LVL_MSK_INTR_LEN      1
#define PACK_INFO_REG_INFO_FRM_LVL_MSK_INTR_OFFSET   1
#define PACK_INFO_REG_INFO_TRANS_END_MSK_INTR_LEN    1
#define PACK_INFO_REG_INFO_TRANS_END_MSK_INTR_OFFSET 0

#define PACK_INFO_REG_INFO_FRM_BPLVL_LEN      3
#define PACK_INFO_REG_INFO_FRM_BPLVL_OFFSET   4
#define PACK_INFO_REG_INFO_FRM_LVL_CFG_LEN    3
#define PACK_INFO_REG_INFO_FRM_LVL_CFG_OFFSET 0

#define PACK_INFO_REG_UFINO_FRM_SIZE_LEN    32
#define PACK_INFO_REG_UFINO_FRM_SIZE_OFFSET 0

#endif // __PACK_INFO_REG_REG_OFFSET_FIELD_H__
